EPC16QC100

Product Summary

• The EPC16QC100 is an enhanced configuration device. The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory of the EPC16QC100 is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete.

Parametrics

EPC16QC100 absolute maximum ratings: (1)VCC Supply voltage With respect to ground: -0.5V to 4.6 V; (2)VI DC input voltage With respect to ground: -0.5V to 3.6 V; (3)IMAX DC VCC or ground current: 100 mA; (4)IOUT DC output current, per pin: -25mA to 25 mA; (5)PD Power dissipation: 360 mW; (6)TSTG Storage temperature No bias: -65℃ to 150℃; (7)TAMB Ambient temperature Under bias: -65℃ to 135℃; (8)TJ Junction temperature Under bias: 135℃.

Features

EPC16QC100 features: (1)Enhanced configuration devices include EPC4, EPC8, and EPC16 devices; (2)Single-chip configuration solution for Stratix series, Cyclone series, APEXII, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), Mercury ACEX1K, and FLEX10K (FLEX 10KE and FLEX 10KA) devices; (3)Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage; (4)On-chip decompression feature almost doubles the effective; (5)configuration density; (6)Standard flash die and a controller die combined into single stacked chip package; (7)External flash interface supports parallel programming of flash and external processor access to unused portions of memory; (8)Flash memory block/sector protection capability via external; (9)flash interface; (10)Supported in EPC16 and EPC4 devices; (11)Page mode support for remote and local reconfiguration with up to eight configurations for the entire system; (12)Compatible with Stratix series Remote System Configuration feature; (13)Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle; (14)Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs; (15)Pin-selectable 2-ms or 100-ms power-on reset (POR) time.

Diagrams

EPC16QC100