XCF16PFSG48C

Product Summary

• The XCF16PFSG48C is an in-system programmable configuration PROM. Available in 1 to 32 Megabit (Mbit) densities, the PROM provides an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The XCF16PFSG48C includes 32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes.

Parametrics

XCF16PFSG48C absolute maximum ratings: (1)VCCINT, Internal supply voltage relative to GND: –0.5 to +2.7 V; (2)VCCO, I/O supply voltage relative to GND: –0.5 to +4.0 V; (3)VCCJ, JTAG I/O supply voltage relative to GND: –0.5 to +4.0 V; (4)VIN, Input voltage with respect to GND VCCO < 2.5V –0.5 to +3.6 –0.5 to +3.6 V; (5)VCCO ≥ 2.5V –0.5 to +5.5 –0.5 to +3.6 V; (6)VTS Voltage applied to High-Z output at VCCO < 2.5V: –0.5 to +3.6 V; at VCCO ≥ 2.5V: –0.5 to +3.6 V; (7)TSTG, Storage temperature (ambient): –65 to +150 ℃; (8)TJ, Junction temperature: +125 ℃.

Features

XCF16PFSG48C features: (1)In-System Programmable PROMs for Configuration of Xilinx FPGAs; (2)Low-Power Advanced CMOS NOR FLASH Process; (3)Endurance of 20,000 Program/Erase Cycles; (4)Operation over Full Industrial Temperature Range(–40℃ to +85℃); (5)IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)Support for Programming, Prototyping, and Testing; (6)JTAG Command Initiation of Standard FPGA Configuration; (7)Cascadable for Storing Longer or Multiple Bitstreams; (8)Dedicated Boundary-Scan (JTAG) I/O Power Supply(VCCJ); (9)I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V; (10)Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages; (11)1.8V supply voltage; (12)Serial or parallel FPGA configuration interface (up to 33 MHz); (13)Available in small-footprint VO48, VOG48, FS48, and FSG48 packages; (14)Design revision technology enables storing and accessing multiple design revisions for; (15)configuration; (16)Built-in data decompressor compatible with Xilinx advanced compression technology.

Diagrams