(China (Mainland))
Product Summary
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The EP1S20F672C7N is the FPGA, which is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. EP1S20F672C7N offers up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).
Parametrics
EP1S20F672C7N absolute maximum ratings: (1)Supply voltage With respect to ground:VCCINT, –0.5 to 2.4 V; (2)DC input voltage:–0.5 to 4.6 V; (3)DC output current, per pin: –25 to 40 mA; (4)Storage temperature No bias: –65 to 150 ℃; (5)Junction temperature BGA packages under bias: 135 ℃.
Features
EP1S20F672C7N features: (1)Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources; (2)Up to 16 global clocks with 22 clocking resources per device region; (3)Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting; (4)Support for numerous single-ended and differential I/O standards; (5)High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps); (6)Support for high-speed networking and communications bus; (7)standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4; (8)Differential on-chip termination support for LVDS.
Diagrams
EP1S20F672C7N
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IC STRATIX FPGA 20K LE 672-FBGA |
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